Semiconductor integrated circuit device
US6423992B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Jun 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.