Circuit for dynamic signal drive strength compensation
US6424186B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for dynamic signal drive strength compensation. A circuit for compensating the drive strength of an output signal includes an output driver stage including a driver circuit and a drive strength control circuit. The driver circuit may be selectively enabled depending upon a drive strength indicator signal. The driver circuit includes a P-channel transistor which has a P input which is controlled by a P-channel control signal. The driver circuit also includes an N-channel transistor which has an N input which is controlled by an N-channel control signal. The drive strength control circuit may generate the respective P-channel and N-channel control signals. The P-channel control signal is prevented from changing while the P-channel transistor is turned on. The N-channel control signal is prevented from changing while the N-channel transistor is turned on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.