Programmable JTAG network architecture to support proprietary debug protocol
US6425101B1 · kind B1 · utility
54Cited by
12References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 30, 1998 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Oct 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318558
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus capable of testing a plurality of JTAG compliant integrated circuits where at least one of the integrated circuits includes an enhanced embedded debug module is described. The apparatus is capable of selectively testing certain of the integrated circuits located at specified locations. In this way, integrated circuits included in a target device having defective or missing integrated circuits can still be tested. The apparatus also allows access to enhanced JTAG debug protocol within a mixed IC (OCDS and non-OCDS) network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.