Area efficient delay circuits
US6425115B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2000 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | May 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a library of cells that can be stored in a computer readable memory and used in the computer-aided design of integrated circuits. Some of the cells in this cell library describe circuits having variable delays. In this cell library, two different cells are able to represent circuits that can be configured to delay signal transmission by different time periods while still being contained within substantially equal areas on a silicon substrate. One way that the cell library allows for such a configuration is if the two cells both represent a delay circuits that contains an n-channel transistor coupled to a p-channel transistor. Each n-channel and p-channel transistor has an n- or p-channel gate respectively, and this gate can be described as having a length and a width. When the length of the n-channel gate in the first delay circuit differs from the length of the n-channel gate in the second delay circuit, the delay time associated with each circuit will also differ. For example, if the length of the n-channel gate in the first circuit is longer than that of the n-channel gate in the second circuit, the first circuit can have a longer delay than the se…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.