Metallurgy for semiconductor devices
US6426558B1 · kind B1 · utility
16Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2001 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | May 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure is described which improves the manufacturability of integrated circuit interconnect and stud contacts in contact with semiconductor substrates and upper levels of metallization. The monolithic structure is formed from a thick layer of refractory metal. A variation in the monolithic structure is in the use of a dual damascene local interconnect portion of the structure which allows the local interconnect to pass over structures previously formed on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.