High performance fully dual-ported, pipelined cache design
US6427191B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1998 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Dec 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The cache design allows two cache requests to be processed simultaneously (dual-ported) and concurrent cache requests to be in-flight (pipelined). The design of the cache allocates a first clock cycle to cache tag and data access and a second cycle is allocated to data manipulation. The memory array circuit design is simplified because the circuits are synchronized to the main processor clock and do not need to use self-timed circuits. The overall logic control scheme is simplified because distinct cycles are allocated to the cache functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.