Dual mask process for semiconductor devices

US6429067B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Joyce C. Liu · Carmel, US
• James C. Brighten · Boise, US
• Jeffrey J. Brown · Palmyra, US
• John W. Golz · Manassas, US
• George A. Kaplita · New Windsor, US
• Rebecca D. Mih · Wappingers Falls, US
• Senthil Srinivasan · Wappingers Falls, US
• Jin J. Wu · Hopewell Junction, US
• Teresa J. Wu · Rexford, US
• Chienfan Yu · Highland Mills, US

Key dates

• Filing date: Jan 17, 2001
• Grant date: Aug 6, 2002
• Expiry date: Jan 17, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.