Method of self-aligning a floating gate to a control gate and to an isolation in an electrically erasable and programmable memory cell, and a cell made thereby

US6429075B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Bing Yeh · Alhambra, US
• Yaw Wen Hu · Cupertino, US

Key dates

• Filing date: Mar 29, 2001
• Grant date: Aug 6, 2002
• Expiry date: Mar 29, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6891

Abstract

An electrically programmable memory cell is of the type having a floating gate and a control gate laterally spaced apart, and both insulated from a substrate. The floating gate and the control gate are made by a self-aligned method wherein, a first layer of silicon dioxide is provided on the substrate. A first layer of polysilicon is then provided on the first layer of silicon dioxide. The first layer of polysilicon is patterned and selective portions are removed. A second layer of silicon dioxide is provided on the patterned first layer of polysilicon. Portions of the second layer of silicon dioxide are selectively masked to define regions in the corresponding first layer of polysilicon which would become the floating gate. The second layer of silicon dioxide is anisotropically etched. The second layer of silicon dioxide is then isotropically etched. The first layer of polysilicon is anisotropically etched to defined the floating gate. Exposed portion of the first layer of polysilicon are then oxidized to form a sharp edge. Silicon dioxide is deposited on the second layer of silicon dioxide and the oxidized exposed portion of the first layer of polysilicon. A second layer of polys…