Semiconductor integrated circuit device
US6429476B2 · kind B2 · utility
16Cited by
4References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2001 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Mar 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Bit lines BL of a DRAM that are narrowed to 0.1 &mgr;m or less are made of two-layered conductive films, in which a W (tungsten) film is deposited on a WN (tungsten nitride) film. For bit lines BL, fewer W atoms diffuse across the interface between the W film and the WN film, within crystal grains, and at grain boundaries of the W film, and no tensile stress exists in the W film. Therefore, high-temperature thermal processing in the capacitor formation process does not cause wiring breaks even when the width of the bit lines BL is narrowed to 0.1 &mgr;m or less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.