Nand flash memory with specified gate oxide thickness
US6429479B1 · kind B1 · utility
4Cited by
4References
19Claims
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Key dates
| Filing date | Mar 9, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Mar 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A single tunnel gate oxidation process for fabricating NAND memory strings where the gate oxide of the select transistors and the floating gate memory transistors are fabricated in a single oxidation step is disclosed. The select gate transistors and the floating gate memory transistors have an oxide thickness of 85 å-105 å. For single tunnel gate approach, a careful selection of the medium doped source/drain region implant conditions is necessary for proper function of the NAND memory string. In one embodiment, the medium doped source/drain region is doped with Arsenic to a concentrations of 1013-1014/cm2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.