Multilayer spiral inductor and integrated circuits incorporating the same
US6429504B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | May 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiple layer inductor structure in which the difference in phase current between upper and lower spiral inductor segments is reduced so as to thereby obtain not only a significant reduction in area but also a substantial increase in self-resonance frequency and a concomitant increase in the operating frequency range. The structure incorporates upper and lower spiral inductor sections, the lower section being disposed on the surface of a semiconductor substrate and the upper section being disposed on the surface of a dielectric layer which separates the respective spiral inductor sections. A plurality of electrically conductive vias interconnect adjacent concentric loop segments of the spiral inductor sections, so that as current flows through the inductor element it passes from one of the upper and the lower inductor sections to the other of the upper and lower inductor sections, alternating between these levels a number of times (i.e., a number less than or equal to the number of concentric segments). Because current flows in the same direction in each of the upper and lower inductor sections, the mutual inductance between the upper and lower inductor sections has a net positi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.