Programmable logic device routing architecture to facilitate register re-timing
US6429681B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 9, 2001 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Feb 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device has registers (“re-timing registers”) associated with interconnection conductors. The re-timing registers are in addition to registers that are conventionally associated with other device elements such as logic and memory cells. Programmable links enable optional data paths through the re-timing registers between disconnected segments of interconnection conductors. Re-timing techniques for optimization of circuit designs seeking to minimize the longest register-to-register path can include positioning of re-timing registers on interconnection conductors. Long interconnection conductors can be used in data paths between device elements with only short segments of interconnection conductors contributing to critical path lengths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.