Inventor · Mountain View, CA, US

Michael D. Hutton

114Patents
16h-index
62Co-inventors
89Inventor score

Filing activity: Mar 2, 2000 → Oct 18, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7135888B1 Programmable routing structures providing shorter timing delays for input/output signals Electricity 180 Expired
US6407576B1 Interconnection and input/output resources for programmable logic integrated circuit devices Electricity 147 Expired
US9106229B1 Programmable interposer circuitry Electricity 134 Active
US7337100B1 Physical resynthesis of a logic design Physics 106 Expired
US7120883B1 Register retiming technique Physics 92 Expired
US7420390B1 Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size Electricity 49 Expired
US6747480B1 Programmable logic devices with bidirect ional cascades Electricity 31 Expired
US7818705B1 Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew Physics 26 Active
US9697318B2 State visibility and manipulation in integrated circuits Electricity 26 Active
US8314636B2 Field programmable gate array with integrated application specific integrated circuit fabric Electricity 25 Active
US7689955B1 Register retiming technique Physics 23 Active
US7469394B1 Timing variation aware compilation Physics 21 Active
US8381142B1 Using a timing exception to postpone retiming Physics 20 Active
US7042248B1 Dedicated crossbar and barrel shifter block on programmable logic resources Physics 19 Expired
US8082526B2 Dedicated crossbar and barrel shifter block on programmable logic resources Physics 17 Active
US7784008B1 Performance visualization system Physics 17 Active
US7133819B1 Method for adaptive critical path delay estimation during timing-driven placement for hierarchical programmable logic devices Physics 16 Expired
US8402408B1 Register retiming technique Physics 15 Active
US9294092B2 Error resilient packaged components Electricity 14 Active
US8072238B1 Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions Electricity 11 Active
US7902864B1 Heterogeneous labs Electricity 11 Expired
US8108812B1 Register retiming technique Physics 10 Active
US6429681B1 Programmable logic device routing architecture to facilitate register re-timing Electricity 10 Expired
US7827433B1 Time-multiplexed routing for reducing pipelining registers Physics 10 Active
US6989689B2 Interconnection and input/output resources for programmable logic integrated circuit devices Electricity 10 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.