Stack-based impulse flip-flop with stack node pre-charge and stack node pre-discharge
US6429711B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/163
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit including a data signal input to receive a data signal, a clock signal input to receive a clock signal, a clocking circuit to generate control clocks, and a multiple input conditional inverter to receive the data signal and control clocks, and to generate an output. The circuit also includes at least one stack node pre-charging transistor coupled to a high signal transfer node in the multiple input conditional inverter and at least one stack node pre-discharging transistor coupled to a low signal transfer node in the multiple input conditional inverter. A keeper circuit receives the output of the multiple input conditional inverter and a buffer circuit receives the output of the multiple input conditional inverter and generates the circuit output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.