Method for fabrication of an MIM capacitor and related structure
US6430028B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Nov 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
According to a disclosed embodiment, an interconnect metal layer is deposited. The interconnect metal layer can be, for example, aluminum, copper, or an aluminum-copper alloy. Then a first dielectric is fabricated over the interconnect metal layer. The first dielectric can be, for example, silicon nitride. A top metal layer is then formed over the first dielectric. The top metal layer can be, for example, titanium nitride. Next, the top metal layer and the first dielectric are patterned and etched to form a capacitor first electrode and a capacitor dielectric. Thereafter a layer of a second dielectric is deposited over the capacitor first electrode and the capacitor dielectric. The second dielectric can be, for example, silicon oxide. Then the second dielectric is etched back, as a result of which spacers covering common sidewalls of the capacitor first electrode and the capacitor dielectric are formed. The spacers protect the capacitor dielectric from being etched during subsequent Processing steps. In one embodiment, a structure fabricated according to the process steps discussed above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.