Arjun Kar-Roy
22Patents
8h-index
14Co-inventors
68Inventor score
Filing activity: May 24, 2000 → Apr 30, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6777777B1 | High density composite MIM capacitor with flexible routing in semiconductor dies | Electricity | 34 | Expired |
| US6430028B1 | Method for fabrication of an MIM capacitor and related structure | Electricity | 23 | Expired |
| US6680521B1 | High density composite MIM capacitor with reduced voltage dependence in semiconductor dies | Electricity | 21 | Expired |
| US7589009B1 | Method for fabricating a top conductive layer in a semiconductor die and related structure | Electricity | 14 | Active |
| US7041569B1 | Method for fabricating a high density composite MIM capacitor with reduced voltage dependence in semiconductor dies | Electricity | 12 | Expired |
| US6411492B1 | Structure and method for fabrication of an improved capacitor | Electricity | 12 | Expired |
| US7078310B1 | Method for fabricating a high density composite MIM capacitor with flexible routing in semiconductor dies | Electricity | 12 | Expired |
| US7897484B2 | Fabricating a top conductive layer in a semiconductor die | Electricity | 9 | Active |
| US7772673B1 | Deep trench isolation and method for forming same | Electricity | 6 | Active |
| US8212331B1 | Method for fabricating a backside through-wafer via in a processed wafer and related structure | Electricity | 5 | Active |
| US8598713B2 | Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation | Electricity | 4 | Active |
| US8098351B2 | Self-planarized passivation dielectric for liquid crystal on silicon structure and related method | Physics | 4 | Active |
| US7704874B1 | Method for fabricating a frontside through-wafer via in a processed wafer and related structure | Electricity | 4 | Active |
| US9887123B2 | Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method | Electricity | 3 | Active |
| US7052966B2 | Deep N wells in triple well structures and method for fabricating same | Electricity | 3 | Expired |
| US9136157B1 | Deep N wells in triple well structures | Electricity | 2 | Expired |
| US9346669B2 | Robust MEMS structure with via cap and related method | Electricity | 2 | Active |
| US9458011B2 | Scalable self-supported MEMS structure and related method | Electricity | 0 | Active |
| US9377350B2 | Light sensor with chemically resistant and robust reflector stack | Physics | 0 | Active |
| US10615071B2 | Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method | Electricity | 0 | Active |
| US9105681B2 | Method for forming deep silicon via for grounding of circuits and devices, emitter ballasting and isolation | Electricity | 0 | Active |
| US10615072B2 | Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.