CMOS boosting circuit utilizing ferroelectric capacitors
US6430093B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2001 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | May 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A boosting circuit for a ferroelectric memory using a NAND-INVERT circuit to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level “0” will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.