Transparent continuous refresh RAM cell architecture
US6430098B1 · kind B1 · utility
5Cited by
11References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2000 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Jul 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.