Functional testing method and circuit including means for implementing said method
US6430720B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1998 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Jun 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention relates to a method of functional testing of a logic circuit and to an integrated circuit for implementing the method. The method includes providing at least one test pattern and the storage of this test pattern in a first test register, this providing step being synchronized by an external clock signal; serially providing of this test pattern to an input of the internal logic circuit, this providing step being synchronized by a test clock signal generated from an internal clock signal; storing, in a second test register connected to the output of the internal logic circuit, at least one resulting pattern generated by the internal logic circuit when the test pattern is provided thereto, this storing being synchronized by the test clock signal; and providing to the outside, by series shifting, of the resulting pattern, this providing step being synchronized by the external clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.