Method for structured layout in a hardware description language
US6430732B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1999 |
| Grant date | Aug 6, 2002 |
| Priority date | — |
| Expiry date | Feb 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for structured layout of design objects in a hardware description language (HDL). Standard features of the HDL are used to specify a first-level design object and the placement of other design objects in the first-level design object. A first-level design object is declared, wherein the first design object has no input or output ports and has one or more slots available for one or more second-level design objects. Values are assigned to attributes of the first-level design object to indicate placement for the second-level design objects within the first-level design object. The second-level design objects are declared as elements within the first-level design object, and the first- and second-level design objects are thereafter compiled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.