Memory cell having an ONO film with an ONO sidewall and method of fabricating same
US6432773B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Apr 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/681
Abstract
A merged two transistor memory cell of an EEPROM, and method of fabricating same, is provided. The memory cell includes a substrate and insulating layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes an ONO stack film that is disposed between the floating gate and the shared gate. In fabricating the memory, the ONO stack film is formed adjacent to the top and side surfaces of the floating gate. The ONO stack film is also formed so as not to be interposed between a potion of the shared gate that is adjacent to the substrate and the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.