Method of manufacturing an interconnect structure having a passivation layer for preventing subsequent processing reactions
US6432814B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Nov 30, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of manufacturing an interconnect structure within a substrate. The method includes forming an opening in a substrate, which may be a dielectric layer having a low k; for example, one where the dielectric constant ranges from about 3.9 to about 1.9. This method further includes forming a passivation layer within the opening and a photoresist within the opening and over the passivation layer. The passivation layer substantially or completely inhibits the diffusion of elements from the substrate that can deactivate a photo acid generator (PAG) within the photoresist, which prevents the photoresist from developing properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.