LVTSCR with a holding voltage that is greater than a DC bias voltage on a to-be-protected node
US6433368B1 · kind B1 · utility
22Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2001 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jan 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/251
Abstract
The holding voltage (the minimum voltage required for operation) of a low-voltage triggering silicon-controlled rectifier (LVTSCR) is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is increased by inserting a voltage drop between the to-be-protected node and the emitter of the pnp transistor of the LVTSCR. As a result, the LVTSCR can be utilized to provide ESD protection to power supply pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.