Vladislav Vashchenko
149Patents
15h-index
44Co-inventors
82Inventor score
Filing activity: Sep 11, 2000 → May 31, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7180379B1 | Laser powered clock circuit with a substantially reduced clock skew | Physics | 262 | Expired |
| US6586317B1 | Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage | Emerging Cross-Sectional Technologies | 27 | Expired |
| US6906357B1 | Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection | Electricity | 23 | Expired |
| US6784029B1 | Bi-directional ESD protection structure for BiCMOS technology | Electricity | 22 | Expired |
| US6433368B1 | LVTSCR with a holding voltage that is greater than a DC bias voltage on a to-be-protected node | Electricity | 22 | Expired |
| US6964907B1 | Method of etching a lateral trench under an extrinsic base and improved bipolar transistor | Electricity | 22 | Expired |
| US6560081B1 | Electrostatic discharge (ESD) protection circuit | Electricity | 20 | Expired |
| US6963091B1 | Spin-injection devices on silicon material for conventional BiCMOS technology | Electricity | 19 | Expired |
| US7023029B1 | Complementary vertical SCRs for SOI and triple well processes | Electricity | 18 | Expired |
| US6852562B1 | Low-cost method of forming a color imager | Electricity | 17 | Expired |
| US7394133B1 | Dual direction ESD clamp based on snapback NMOS cell with embedded SCR | Electricity | 16 | Expired |
| US6407445B1 | MOSFET-based electrostatic discharge (ESD) protection structure with a floating heat sink | Electricity | 16 | Expired |
| US7910951B2 | Low side zener reference voltage extended drain SCR clamps | Electricity | 16 | Active |
| US7651897B2 | Integrated circuit with metal heat flow path coupled to transistor and method for manufacturing such circuit | Electricity | 15 | Active |
| US6985386B1 | Programming method for nonvolatile memory cell | Physics | 15 | Expired |
| US7005388B1 | Method of forming through-the-wafer metal interconnect structures | Electricity | 14 | Expired |
| US7639464B1 | High holding voltage dual direction ESD clamp | Electricity | 14 | Expired |
| US7119431B1 | Apparatus and method for forming heat sinks on silicon on insulator wafers | Electricity | 14 | Expired |
| US7141831B1 | Snapback clamp having low triggering voltage for ESD protection | Electricity | 14 | Expired |
| US7754540B2 | Method of forming a SiGe DIAC ESD protection structure | Electricity | 14 | Active |
| US7145187B1 | Substrate independent multiple input bi-directional ESD protection structure | Electricity | 14 | Expired |
| US6717219B1 | High holding voltage ESD protection structure for BiCMOS technology | Electricity | 14 | Expired |
| US6862216B1 | Non-volatile memory cell with gated diode and MOS transistor and method for using such cell | Electricity | 13 | Expired |
| US7910950B1 | High voltage ESD LDMOS-SCR with gate reference voltage | Electricity | 13 | Active |
| US6797555B1 | Direct implantation of fluorine into the channel region of a PMOS device | Electricity | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.