Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication
US6433427B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2001 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jan 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level package that incorporates dual stress buffer layers for achieving I/O pad redistribution and a method for forming the package are disclosed. In the package, a first stress buffer layer and a second stress buffer layer are sequentially deposited on top of an IC die by a method such as spin coating, laminating, screen printing or stencil printing of an elastic material which has a Young's modulus of less than 10 MPa. A suitable thickness for the first and the second stress buffer layer is between about 10 &mgr;m and about 70 &mgr;m. Metal traces are formed on top of the first and the second stress buffer layer for connecting a first plurality of I/O pads and a second plurality of I/O pads to achieve I/O redistribution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.