Semiconductor device with misaligned via hole
US6433433B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jun 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76886
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate, e.g., a part of a silicon wafer having an oxide layer disposed thereon. A metal stack is disposed over the semiconductor substrate and a dielectric layer is disposed over the metal stack. The dielectric layer has a via hole formed therein that is misaligned with the metal stack such that a portion of the via hole extends beyond the top of the metal stack and exposes at least a portion of one of the sidewalls of the metal stack. A sidewall cap layer is formed on the exposed portion of the sidewall of the metal stack. The sidewall cap layer is configured to resist substantial penetration of WF6 during chemical vapor deposition of tungsten. The sidewall cap layer may be a nitrided layer or a layer of a dielectric material. A conductive material comprised of tungsten is disposed in and substantially fills the via hole. Methods for making a conductive via in a semiconductor device are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.