Methods and apparatus for optimizing semiconductor inspection tools
US6433561B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Sep 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/2817
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a method of inspecting a sample. At least a portion of the sample is illuminated. Signals received from the illuminated portion are detected, and the detected signals are processed to find defects present on the sample. The processing of the detected signals is optimized, at least in part, based upon results obtained from voltage contrast testing. In one implementation, the illumination is an optical illumination. In another embodiment, the processing comprises automated defect classification, and setup of the automated classification is optimized using the results obtained from voltage contrast testing. In another implementation, the results relate to a probability that a feature present on the sample represents an electrical defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.