CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching
US6433583B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jun 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The switch circuit receives a first supply voltage and a second supply voltage different from each other; a control input receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage supplied by the second supply voltage and defining the output of the circuit; a feedback inverter stage supplied by the second supply voltage and including a top transistor and a bottom transistor defining an intermediate node and having respective control terminals. The control terminal of the top transistor is connected to the output node, the control terminal of the bottom transistor is connected to the control input, and the intermediate node is connected to the input of the driving inverter stage. An activation element helps switching of the intermediate node from the second supply voltage to ground; current limiting transistors are arranged in the inverter stages to limit the current flowing during switching and to reduce the consumption of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.