Overvoltage-tolerant interface for integrated circuits
US6433585B1 · kind B1 · utility
31Cited by
84References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Sep 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.