Patent · US Expired

Circuit for data signal recovery and clock signal regeneration

US6433599B1 · kind B1 · utility

9Cited by

7References

6Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Dirk Friedrich · Munich, DE
Michael Rozmann · Eichenau, DE

Key dates

Filing date	Mar 19, 2001
Grant date	Aug 13, 2002
Priority date	—
Expiry date	Mar 19, 2021

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/033
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

The data and clock regeneration circuit can be completely integrated in a chip. The circuit has, in series, two independent PLL regulating stages which are optimally adjustable separately. The first PLL regulating stage has a large bandwidth and is optimized for maximum jitter tolerance and the second PLL regulating stage has a small bandwidth and is optimized for minimum jitter transfer. The circuit is suitable for use, for example, in transceivers for ATM, SONET, and SDH applications with signal transmission links in the Gbit range.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.