Silicon-on-insulator CMOS circuit
US6433620B1 · kind B1 · utility
4Cited by
14References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Nov 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Silicon-On-Insulator (SOI) CMOS circuit includes a plurality of PMOS transistors connected in series to each other and at least one NMOS transistor connected to one of the PMOS transistors. The NMOS transistor has its body connected to a low reference potential having a value of ground. The SOI CMOS circuit further includes a body potential generating circuit which generates a body potential between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential. The body potential generating circuit applies the high potential to the bodies of the PMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.