Method and apparatus for self-calibration and fixed-pattern noise removal in imager integrated circuits
US6433822B1 · kind B1 · utility
49Cited by
4References
15Claims
0Family size
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Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N17/002
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An architecture for self-calibration and fixed-pattern noise removal in imager chips. The column-to-column fixed pattern noise and/or pixel-to-pixel fixed pattern noise is determined through a self-calibration operation. During operation of the imager chip, when a value of a pixel is read, the read value is compensated with the fixed-pattern noise corresponding to either the column fixed pattern noise corresponding to the column having the pixel from which the value was read or to the pixel fixed pattern noise corresponding to the pixel from which the value was read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.