Method and system for generation and distribution of supply voltages in memory systems
US6434044B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2001 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Feb 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are described. The various voltage levels can be produced by voltage generation circuitry (e.g., charge pump and/or regulator circuitry) within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect, charge pump and/or regulator circuits are provided within at most one of the memory blocks of a memory system (unless back-ups are provided for fault tolerance), and a power bus is used to distribute the generated voltage levels to other of the memory blocks. According to another aspect, a memory controller generates multiple supply voltage levels that are distributed (e.g., via a power bus) to each of the memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.