Two-phase charge-sharing data latch for memory circuit
US6434069B1 · kind B1 · utility
6Cited by
3References
4Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 16, 2000 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jun 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read data latch circuit that requires only two phases to execute a data read cycle. The date read lines and data latch lines are precharged and equalized during the data read cycle. A separate phase for equalizing the data latch nodes is eliminated. Rather, the data latch nodes charge share with the previously equalized and precharged data lines. The latch nodes are effectively precharged and equalized, as the capacitance on the data lines is much larger than the capacitance on the data latch nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.