John D. Heightley
18Patents
6h-index
6Co-inventors
59Inventor score
Filing activity: Jun 30, 1980 → Nov 20, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4355377A | Asynchronously equillibrated and pre-charged static ram | Physics | 80 | Expired |
| US6415374B1 | System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM) | Physics | 40 | Expired |
| US4363111A | Dummy cell arrangement for an MOS memory | Physics | 26 | Expired |
| US7474136B2 | Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory device | Physics | 12 | Active |
| US6445621B1 | Dynamic data amplifier with built-in voltage level shifting | Physics | 10 | Expired |
| US6339541B1 | Architecture for high speed memory circuit having a relatively large number of internal data lines | Electricity | 8 | Expired |
| US6434069B1 | Two-phase charge-sharing data latch for memory circuit | Physics | 6 | Expired |
| US6359487B1 | System and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6469559B2 | System and method for eliminating pulse width variations in digital delay lines | Electricity | 6 | Expired |
| US6339354B1 | System and method for eliminating pulse width variations in digital delay lines | Electricity | 5 | Expired |
| US6741488B1 | Multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output assignments in an integrated circuit memory device | Physics | 4 | Expired |
| US7071745B2 | Voltage-controlled analog delay locked loop | Electricity | 4 | Expired |
| US7876137B2 | Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devices | Electricity | 3 | Active |
| US7167052B2 | Low voltage differential amplifier circuit for wide voltage range operation | Electricity | 3 | Expired |
| US7102439B2 | Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levels | Electricity | 3 | Expired |
| US7061322B2 | Low voltage differential amplifier circuit and bias control technique enabling accommodation of an increased range of input levels | Electricity | 3 | Expired |
| US7518425B2 | Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices | Electricity | 3 | Active |
| US7218564B2 | Dual equalization devices for long data line pairs | Physics | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.