System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching scheme
US6434641B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 1999 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some requests presented to the main memory can not be completed immediately because the most recent copy of the requested data must be retrieved from another cache memory. These requests are stored in a temporary storage structure and identified as “deferred” requests. Subsequently, predetermined ones of the memory requests that are requesting access to the same main memory address as is being requested by any deferred request are also deferred. When a data retrieval operation is completed, an associated request is designated as undeferred so that processing for that request may be completed, and the request may be removed from the temporary storage structure. According to one aspect of the invention, all deferred requests requesting access to the same main memory address are stored as a linked list of requests in the temporary storage structure. Requests are processed by main memory in a first-in, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.