Transistor having an improved gate structure and method of construction
US6436746B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1999 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jan 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation dielectric layer (26) may be formed adjacent the primary insulation layer (22). The disposable gate (24) may be removed to expose a portion of the primary insulation layer (22). The exposed portion of the primary insulation layer (22) may be removed to expose a portion of the substrate (12). The primary insulation layer (22) may be selectively removable relative to the isolation dielectric layer (26). A gate insulator (30) may be formed on the exposed portion of the substrate (12). A gate (32) may be formed adjacent the gate insulator (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.