Process for annealing semiconductors and/or integrated circuits
US6436799B1 · kind B1 · utility
15Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Sep 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.