Manuj Rathor
22Patents
4h-index
37Co-inventors
63Inventor score
Filing activity: Jun 15, 1999 → Nov 30, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6818558B1 | Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices | Electricity | 143 | Expired |
| US6372634B1 | Plasma etch chemistry and method of improving etch control | Electricity | 15 | Expired |
| US6436799B1 | Process for annealing semiconductors and/or integrated circuits | Electricity | 15 | Expired |
| US7323377B1 | Increasing self-aligned contact areas in integrated circuits using a disposable spacer | Electricity | 7 | Expired |
| US10141504B2 | Methods and processes for forming devices from correlated electron material (CEM) | Electricity | 4 | Active |
| US7468525B2 | Test structures for development of metal-insulator-metal (MIM) devices | Electricity | 3 | Active |
| US10672982B1 | Fabrication of correlated electron material (CEM) devices | Electricity | 3 | Active |
| US8093698B2 | Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device | Electricity | 2 | Active |
| US6624052B2 | Process for annealing semiconductors and/or integrated circuits | Electricity | 2 | Expired |
| US8089113B2 | Damascene metal-insulator-metal (MIM) device | Electricity | 1 | Active |
| US8717803B2 | Metal-insulator-metal-insulator-metal (MIMIM) memory device | Electricity | 1 | Active |
| US7772077B2 | Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region | Electricity | 1 | Active |
| US8093680B1 | Metal-insulator-metal-insulator-metal (MIMIM) memory device | Electricity | 1 | Active |
| US8803120B2 | Diode and resistive memory device structures | Electricity | 1 | Active |
| US11075339B2 | Correlated electron material (CEM) devices with contact region sidewall insulation | Electricity | 0 | Active |
| US8232175B2 | Damascene metal-insulator-metal (MIM) device with improved scaleability | Electricity | 0 | Active |
| US8035099B2 | Diode and resistive memory device structures | Electricity | 0 | Active |
| US9343666B2 | Damascene metal-insulator-metal (MIM) device with improved scaleability | Electricity | 0 | Active |
| US8084770B2 | Test structures for development of metal-insulator-metal (MIM) devices | Electricity | 0 | Active |
| US8373148B2 | Memory device with improved performance | Electricity | 0 | Active |
| US6969689B1 | Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices | Electricity | 0 | Expired |
| US10707415B2 | Methods and processes for forming devices from correlated electron material (CEM) | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.