Method of fabricating a DRAM cell configuration
US6436836B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Apr 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0385
Abstract
A depression is produced in a substrate for a capacitor of a memory cell of the DRAM cell configuration. An insulation and a storage node of the capacitor are produced in the depression. A spacer made of silicon is produced above the storage node. A first part of the spacer is doped by inclined implantation. The spacer is patterned by utilizing the different doping of the first part of the spacer. With the aid of the patterned spacer as a mask, the storage node and the insulation are altered in such a way that the storage node directly adjoins the substrate only in a limited patch of a sidewall of the depression and is otherwise isolated from the substrate by the insulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.