Low dielectric constant sidewall spacer using notch gate process
US6437377B1 · kind B1 · utility
12Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jan 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is significantly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.