Victor Ku
19Patents
12h-index
42Co-inventors
78Inventor score
Filing activity: Jan 10, 1974 → Jun 24, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6921711B2 | Method for forming metal replacement gate of high performance | Electricity | 119 | Expired |
| US7041538B2 | Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS | Electricity | 110 | Expired |
| US7056794B2 | FET gate structure with metal gate electrode and silicide contact | Electricity | 85 | Expired |
| US3999163A | Secondary storage facility for data processing systems | Physics | 50 | Expired |
| US7029966B2 | Process options of forming silicided metal gates for advanced CMOS devices | Electricity | 47 | Expired |
| US7326610B2 | Process options of forming silicided metal gates for advanced CMOS devices | Electricity | 29 | Expired |
| US6677646B2 | Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS | Electricity | 23 | Expired |
| US6544874B2 | Method for forming junction on insulator (JOI) structure | Electricity | 22 | Expired |
| US6506649B2 | Method for forming notch gate having self-aligned raised source/drain structure | Electricity | 17 | Expired |
| US7056782B2 | CMOS silicide metal gate integration | Electricity | 15 | Expired |
| US6528363B2 | Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch | Electricity | 13 | Expired |
| US6437377B1 | Low dielectric constant sidewall spacer using notch gate process | Electricity | 12 | Expired |
| US6927117B2 | Method for integration of silicide contacts and silicide gate metals | Electricity | 8 | Expired |
| US6184119A | Methods for reducing semiconductor contact resistance | Electricity | 8 | Expired |
| US6974736B2 | Method of forming FET silicide gate structures incorporating inner spacers | Electricity | 6 | Expired |
| US6383918B1 | Method for reducing semiconductor contact resistance | Electricity | 5 | Expired |
| US7411227B2 | CMOS silicide metal gate integration | Electricity | 5 | Expired |
| US7655557B2 | CMOS silicide metal gate integration | Electricity | 3 | Active |
| US7635648B2 | Methods for fabricating dual material gate in a semiconductor device | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.