Erasing device and method for flash memory
US6438039B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2001 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jul 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase device and a method of erasing data from a flash memory. The erase device includes a shift control signal transmission terminal, an erase control group and a pulse control group. The shift control signal transmission terminal is used for transmitting a shift control signal. The erase control group includes a plurality of serially connected erase controllers. Each erase controller corresponds to a memory block. Each of the erase controllers contains a shift register, a receiving terminal and an output terminal. The receiving terminal of the first erase controller receives a shift control signal sent from the shift control signal transmission terminal. The receiver terminal of a subsequent erase controller connects electrically with the output terminal of the previous erase controller. In addition, the shift register contains a shift control signal received from the receiving terminal. The shift control signal is used for directing the erasure of memory block data that correspond to the erase controller. The pulse control signal group controls the sending and the receiving of shift control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.