Nonvolatile memory and high speed memory test method
US6438048B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Sep 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device has a signature code generator generating an new signature code as a function of data read from the cell array and the previously calculated signature code. Data are read in sequence, using an internal clock generated by an internal clock oscillator. In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code is variable in dynamic way; at the end of memory scanning, the signature code is compared to an expected result. Thus, testing may be performed at Wafer Sort Test Level, reading the memory cells at the memory operative speed, so as to ensure an early, fast and thorough detection of faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.