Generating partition corresponding real address in partitioned mode supporting system
US6438671B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1999 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jul 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor supports logical partitioning of a computer system. Logical partitions isolate the real address spaces of processes executing on different processors and the hardware resources that include processors. However, this multithreaded processor system can dynamically reallocate hardware resources including the processors among logical partitions. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not. In the preferred embodiment, instruction addresses from either active or dormant threads can be pre-fetched in anticipation of execution. In the preferred embodiment, the processor supports different environments which use the hyper…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.