IC substrate noise modeling with improved surface gridding technique
US6438733B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Jan 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for performing surface modeling of a substrate for the purpose of characterizing the substrate, which includes initially dividing said substrate surface into a plurality of local partitions and thereafter forming divisions from said plurality of local partitions. The technique includes positioning a first component at a first location on said substrate surface, thereby creating additional divisions within one of said plurality of local partitions. The method further includes promoting said one of said plurality of local partitions to a global partition and forming local partitions within said one of said plurality of local partitions if a number of divisions within said one of said plurality of local partitions exceeds a predefined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.