Semiconductor device with elements surrounded by trenches
US6439514B1 · kind B1 · utility
17Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2000 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Jan 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/127
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Pch-MOS transistors to which a power supply potential is applied are respectively surrounded by first trenches, and Nch-MOS transistors to which a ground potential is applied are respectively surrounded by second trenches. The first trenches are surrounded by a third trench, and the second trenches are surrounded by a fourth trench. A silicon layer existing inside the third trench is set at the power source potential. The silicon layer existing between the third and fourth trenches are set at a floating state. Accordingly, each thickness of oxide layers filling the trenches can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.