Patent · US Expired

Method of measuring combined critical dimension and overlay in single step

US6440759B1 · kind B1 · utility

5Cited by

8References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Martin Commons · Stormville, US
Tobias Mono · Dresden, DE
Velt Klee · Pleasant Valley, US
John Pohl · Mission Viejo, US
Paul Wensley · West Bromwich, GB

Key dates

Filing date	Jun 29, 2001
Grant date	Aug 27, 2002
Priority date	—
Expiry date	Jun 29, 2021

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3011
WIPO fieldOptics
WIPO sectorInstruments

Abstract

A semiconductor wafer structure in a overlay pattern that permits determination of overlay and critical dimension features by CD SEM in a single pass along a given axis, comprising:a) a center feature section that provides a critical dimension point along a given axis;b) plurality of smaller sections positioned adjacent to the center feature section along the given axis that include a plurality of spaces between each of the plurality of smaller sections; andc) a plurality of displacement lines adjacent to the plurality of the smaller sections to displace a plurality of spaces.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.