Vertical MOSFET
US6440793B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2001 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Apr 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.