Structure of stacked integrated circuits
US6441496B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Jan 23, 2001 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Jan 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The structure of stacked integrated circuits includes a substrate, a lower integrated circuit, a plurality of wirings, an adhesive layer, and an upper integrated circuit. The substrate has a first surface formed with signal input terminals, and a second surface formed with signal output terminals. The lower integrated circuit has a first surface and a second surface. The first surface is adhered to the first surface of the substrate while the second surface is formed with a plurality of bonding pads. The wirings have first ends and second ends. The first ends are electrically connected to the bonding pads of the lower integrated circuit while the second ends are electrically connected to the signal input terminals of the substrate. The adhesive layer is coated on the second surface of the lower integrated circuit and includes adhesive agent and filling elements. The upper integrated circuit is stacked above the second surface of the lower integrated circuit with the adhesive layer inserted between the upper and lower integrated circuit. The lower integrated circuit is adhered to the upper integrated circuit by the adhesive agent. A predetermined gap is formed between the lower and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.